Applicant hereby incorporates by reference Japanese Application No. 2001-063103, filed Mar. 7, 2001, in its entirety.
1. Technical Field
The present invention relates to non-volatile semiconductor memory devices, and includes non-volatile semiconductor memory devices in which three kinds of data can be written and read at one memory cell unit.
2. Related Art
Non-volatile semiconductor memory devices have certain desired characteristics, for example, they are better suited for development towards greater capacity than DRAMs and SRAMs, and are also capable of high-speed access.
In particular, in recent years, non-volatile semiconductor memory devices whose memory capacity can be readily expanded and in which digitized image data and voice data can be more efficiently written and read are required.
Embodiments relate to a non-volatile semiconductor memory device including a semiconductor substrate and an impurity region and an element isolation region formed in the semiconductor substrate. The device also includes first and second memory elements mutually isolated by the element isolation region. The impurity region includes a first impurity diffusion layer and a second impurity diffusion layer. The first and second memory elements each include a gate dielectric layer, a floating gate, a selective oxide dielectric layer and a third impurity diffusion layer, and also include a common intermediate dielectric layer and a common control gate, and also are connected to the first and second impurity diffusion layers. The third impurity diffusion layer located in each of the first and second memory elements includes a channel region, and an impurity concentration of the third impurity diffusion layer located in the first memory element is different from an impurity concentration of the third impurity diffusion layer located in the second memory element.
Embodiments also relate to a non-volatile semiconductor memory device including a semiconductor substrate and an impurity region and an element isolation region formed in the semiconductor substrate. The device also includes first and second memory elements mutually isolated by the element isolation region. The impurity region includes a first impurity diffusion layer and a second impurity diffusion layer. The first memory element and the second memory element each include a gate dielectric layer, a floating gate, a selective oxide dielectric layer and a third impurity diffusion layer, and also include a common intermediate dielectric layer and a common control gate, and also are connected to the first and second impurity diffusion layers. The first impurity diffusion layer is electrically connected to a bit line. The third impurity diffusion layer in each of the first and second memory elements includes a channel region. A threshold voltage of the first memory element and a threshold voltage of the second memory element are set at different values.
Embodiments also relate to a method for manufacturing a non-volatile semiconductor memory device including a first memory element and a second memory element, the method for manufacturing a non-volatile semiconductor memory device including: (a) forming an element isolation region in a semiconductor substrate to isolate the first memory element from the second memory element; (b) introducing an impurity in each of two regions isolated by the element isolation region in the semiconductor substrate to thereby form a third impurity diffusion layer in the first memory element in one of the two regions and to form a third impurity diffusion layer in the second memory element in another region of the two regions, wherein the third impurity diffusion layer in each of the first and second memory elements is formed such that an impurity concentration of the third impurity diffusion layer in the first memory element and an impurity concentration of the third impurity diffusion layer in the second memory element are different from each other; (c) forming a gate dielectric layer, a floating gate and a selective oxide dielectric layer for each of the first memory element and the second memory element in each of the two regions isolated by the element isolation region on the semiconductor substrate; (d) successively depositing a dielectric layer for forming an intermediate dielectric layer and a conduction layer and then patterning the dielectric layer and the conduction layer into a specified shape to form an intermediate dielectric layer and a control gate commonly shared by the first memory element and the second memory element; and (e) introducing an impurity into a specified region of the semiconductor substrate to form an impurity region that includes the first and second impurity diffusion layers, to thereby form the first memory element and the second memory element.
Embodiments also include a method for manufacturing a non-volatile semiconductor memory device including a first memory element and a second memory element, the method for manufacturing a non-volatile semiconductor memory device comprising the steps of: (a) forming an element isolation region in a semiconductor substrate to isolate the first memory element from the second memory element, and then successively forming a dielectric layer for forming a gate dielectric layer and a conduction layer for forming a floating gate; (b) introducing an impurity in each of two regions isolated by the element isolation region in the semiconductor substrate to thereby form a third impurity diffusion layer in the first memory element in one of the two regions and to form a third impurity diffusion layer in the second memory element in another region of the two regions, wherein the third impurity diffusion layer in each of the first and second memory elements is formed such that an impurity concentration of the third impurity diffusion layer in the first memory element and an impurity concentration of the third impurity diffusion layer in second memory element are different from each other; (c) selectively oxidizing a part of the conduction layer for forming a floating gate to thereby form a selective oxide dielectric layer for the first memory element and the second memory element, and then patterning the dielectric layer for forming a gate dielectric layer and the conduction layer for forming a floating gate into a specified shape, to thereby form a gate dielectric layer and a floating gate for each of the first memory element and the second memory element in the respective two regions isolated by the element isolation region on the semiconductor substrate; (d) successively depositing a dielectric layer for forming an intermediate dielectric layer and a conduction layer for forming a control gate and then patterning the dielectric layer and the conduction layer for forming a control gate into a specified shape to form an intermediate dielectric layer and a control gate commonly shared by the first memory element and the second memory element; and (e) introducing an impurity into a specified region of the semiconductor substrate to form an impurity region that includes the first and second impurity diffusion layers, to thereby form the first memory element and the second memory element.
Embodiments also relate to a method for manufacturing a non-volatile semiconductor memory device including a first memory element in a first memory element region and a second memory element in a second memory element region. The method includes providing a semiconductor substrate including a first memory element region and a second memory element region. The method also includes forming a third impurity diffusion layer in each of the first and second memory element regions, wherein an impurity concentration of the third impurity diffusion layer in the first memory element region is different from an impurity concentration of the third impurity diffusion layer in the second memory element region. The method also includes forming a gate dielectric layer, a floating gate and a selective oxide dielectric layer in each of the first memory element region and the second memory element region. The method also includes depositing a dielectric layer and depositing a conduction layer and patterning the dielectric layer and the conduction layer to form an intermediate dielectric layer and a control gate commonly shared by the first memory element and the second memory element. In addition, the method includes forming first and second impurity diffusion layers in selected regions of the semiconductor substrate.
In an embodiment related to that described in the paragraph above, forming the third impurity diffusion layer in each of the first and second memory element regions may be carried out prior to forming the gate dielectric layer, the floating gate, and the selective oxide dielectric layer in each of the first and second memory element regions. In another embodiment related to that described in the paragraph above, forming the third impurity diffusion layer in each of the first and second memory element regions may be carried out after forming the gate dielectric layer, the floating gate, and the selective oxide dielectric layer in each of the first and second memory element regions.